RESEARCH EVIDENCE
See what changed, what it cost and how each comparison was calculated.
LATEST SOURCE REVIEW / 17 OCTOBER 2026
Independent review checked 2,160 complete protocol jobs across 120 named references and all 1,440 fixed design candidates. All 1,440 candidates miss the saved tight deadline. The separate strict core-floor test leaves 15 candidates unresolved.
Next work is to complete the energy ledgers and include the cost of a circuit that calculates each CRC byte.
Review scope, independent verdict and exact sources →Joint model and latest functional stage · review cutoff 17 October 2026
The complete-job model counts retained, removed, added and shared costs once. Both FI and the strongest tested ordinary controls receive compatible ordinary improvements. The results apply to the specified computational jobs, assumed energy laws and service boundaries. Here, nominal means the main modeled operating point.
Finished bounded model review: all 120 references compared, with 13 nominal wins, 100 ties and 7 unmatched against the strongest tested ordinary controls. No strict robust or tight-inclusive positive-saving winner. Shared and added costs are counted in the joint ledger.
The guarded implementation completed 12 finite vendor-software simulation profiles without annotated route delays. Function/state checks passed and all six intended fault controls were detected. Public latency is 23 clock cycles, 16 more than the prior seven-clock source. Mapped timing, routed power and new whole-device savings remain unqualified.
The earlier backend’s seven-clock result remains in the historical record. The newer guarded source has 23 clocks of functional latency; its power and timing remain unqualified.
The best nominal reference combines compact streaming, clock-gated logic and a one-byte DMA wrapper in one cost calculation. The FIR, recorder and sensing studies have separate workloads and budgets.
Rows are ordered by nominal energy saving against the strongest tested ordinary control. Every row fails the registered test for a positive saving across the required conditions. The last column shows the worst tested energy change for that same nominal installation.
| Reference job | Nominal energy saved | Completion-time change | Worst tested energy change |
|---|---|---|---|
| D027 · Low-power Wi-Fi client electronics | 0.2563% | +51.49% | +0.4356% energy |
| D050 · Airframe health-data reduction | 0.1259% | +4.07% | +1.1896% energy |
| D095 · GNSS interference monitoring | 0.1259% | +4.07% | +1.1896% energy |
| D037 · Wearable sensor hub | 0.1242% | -28.70% | +1.1896% energy |
| D076 · Rail traction condition monitoring | 0.0862% | +4.07% | +0.8152% energy |
| D118 · Seismic field-array data pipeline | 0.0862% | +4.07% | +0.8152% energy |
| D120 · Observatory adaptive-optics actuation | 0.0808% | +33.25% | +1.4747% energy |
| D043 · Spacecraft payload telemetry reduction | 0.0594% | +3.95% | +0.9803% energy |
| D099 · Public-safety radio evidence recorder | 0.0309% | +3.95% | +0.5095% energy |
| D030 · RF instrument waveform linearization | 0.0308% | +65.84% | +0.0968% energy |
| D019 · Magnetic-bearing controller model | 0.0103% | +43.01% | +0.2022% energy |
| D015 · BLDC commutation controller | 0.0035% | +37.37% | +0.0679% energy |
| D072 · EV traction-inverter control | 0.0009% | +37.74% | +0.0170% energy |
The best nominal Wi-Fi reference finishes within its 8 ms limit and fails the separate 1 microsecond stress limit. No fixed candidate met both positive-saving and feasibility requirements across the full core plus tight grid. Seven comparisons have missing baselines or feasibility gaps, so their saving percentages remain unavailable.
The reviewed recorder allocation falls 19.96884% when the same full input history is included: 1,453,784,064 → 1,163,480,256 bytes. Its 25.17568% recorder-only reduction removes the same 290,303,808 bytes. Writes fall 10.7143%, reads 17.6471% and timing-record checksum steps 60%; these are separate axes. Required commit/restart, recovery, durability, clock and physical service remain to be qualified for a complete installation.
The sensing energy model includes a 50% reading-energy share and 3% planning cost. Eight selected cases save 3.25–23.04% versus equal counts; another saves 1.17%, while three equal-noise cases cost 3% more. Exact ordinary planners match the allocation.
If sensing is 20% of whole-phone energy and the other 80% stays fixed with no further costs, the selected sensing range becomes 0.65–4.61% less phone energy and 0.65–4.83% longer battery life with the same battery. Battery downsizing is an alternative use of the saving.
Application budgets for every target
Concise joint results and product coverage · All 120 references; cost ledgers for the 13 nominal wins
Matched modeled power · independent AI review · 16 October 2026
Vivado’s power model puts FI’s hybrid 81-tap receive-channel filter at 310 mW while active, compared with 319 mW for the selected vendor transposed mapping at 25°C. Both use an AMD Artix-7 xc7a35tcpg236-1 FPGA. The modeled reduction is 9 mW, or 2.82%, of total active FPGA power. At 85°C, 424 → 415 mW gives a 2.12% reduction.
| Same declared filter job | Selected vendor mapping | FI hybrid |
|---|---|---|
| Active total power, 25°C | 319 mW | 310 mW |
| Idle total power, 25°C | 161 mW | 162 mW |
| Active total power, 85°C | 424 mW | 415 mW |
| Idle total power, 85°C | 266 mW | 267 mW |
| Active dynamic power | 247.5 mW | 238.5 mW |
| Idle dynamic power | 93 mW | 93 mW |
| Logic tables / ordinary registers | 48 / 330 | 964 / 929 |
| DSP arithmetic blocks / slices | 81 / 162 | 40 / 579 |
| Latency | 16 clock cycles | 46 clock cycles |
FI uses 50.62% fewer DSP arithmetic blocks, trading them for about 20.08 times as many logic tables and 2.82 times as many ordinary registers. Both designs target 100 million real samples per second at 100 MHz and fit the declared 512-cycle latency ceiling. Their implementation remains to be qualified.
Suppose the original 319 mW FPGA accounts for 25% of a device’s 1.276 W active power. Substituting the modeled 310 mW FPGA gives 1.267 W, a reduction of 0.7053%, rounded to 0.71%. This budget holds all other power fixed and adds no integration power. Idle FPGA power rises 1 mW.
The filter takes signed 16-bit Q15 inputs and 16-bit Q19 coefficients. Its exact output has 34 fractional bits, with no rounding. Synthetic 4,096-point I and Q traces were tested separately as real paths. Four signed vendor mappings were compared; the transposed area and speed versions tied on the reported power rows. FI v046 takes 46 cycles, compared with 16 for the reference.
Vivado 2023.2.2 used typical process conditions at fixed 25°C or 85°C. Independent checks confirmed matching activity at the designs’ inputs and outputs; internal activity was inferred. The reported 2.82% total-active and 3.64% active-dynamic reductions use rounded report values. Model uncertainty is unquantified. The idle case holds the design in its reset-idle state.
Interpolating between the latest rounded active and idle totals gives a vendor-minus-FI difference of (10 × active fraction − 1) mW. That calculation breaks even at 10% active time. It excludes transitions, temperature changes and other integration costs. The reports are rounded to 1 mW, and uncertainty in the crossing is unquantified.
Routed functional checks passed and static timing reports were positive, but timing through the native ACOUT paths used by the design remains unresolved. The newer version with a common wrapper passed functional checks; it has no accepted routed power result yet.
The finished 120-reference joint study selected 13 nominal energy wins, 100 ties and seven unmatched comparisons, with no robust positive-saving winner.
Preliminary routed core results · independent AI review · 15 October 2026
A digital filter combines recent inputs to produce each output. FI revised a fixed 16-tap finite impulse response (FIR) filter to use 199 logic tables instead of 339 and 503 ordinary registers instead of 538. Both versions use seven digital signal-processing blocks. Against the paired reference, the revised core uses 41.30% fewer logic tables and 6.51% fewer registers.
The target chip is an xc7a35tcpg236-1 field-programmable gate array (FPGA), whose logic can be configured. Its lookup tables (LUTs) hold small logic functions, registers hold values between clock steps, and digital signal-processing (DSP) blocks perform arithmetic. The counts below come from vendor tools for one filter core.
| Core | Logic tables | Ordinary registers | DSP blocks |
|---|---|---|---|
| Paired reference P0 | 339 | 538 | 7 |
| Revised P9_logic3 | 199 | 503 | 7 |
| Alternative P9 | 165 | 419 | 8 |
All three retain exact 26-bit outputs from 16-bit inputs, seven stages and one input per clock under a 100 MHz timing constraint. The alternative P9 trades fewer logic tables and registers for one extra DSP block.
Vendor tools routed each core in isolation to produce these preliminary counts. Independent AI review inspected the source reports, finite integer checks, register-transfer-level (RTL) simulations and width bounds. RTL describes how values move between circuit registers.
The tested isolation change added 16 logic tables and 48 ordinary registers to P9, which still used eight DSP blocks. Review accepted no useful isolation benefit for that integration.
P9_logic3 still lacks qualified activity-based power, throughput and wider product-fit results.
In a separate three-channel sensing model, 12 readings meet the old balanced 13-reading quality limit, but variance is 8.580858% above the optimized 13-reading plan. A capable ordinary exact planner can match the allocation. In a separate count-and-rail energy example, the combined change uses 8/1943 (0.411734%) more energy than the ordinary lower-rail option under a chosen 25% affected share and separate 1% plus 1% costs.
In the separate software accounting review, FI was slower than capable ordinary gmpy2 in all 26 preserved first-call and warm groups. H22 covers 2,500 cases against the prior FI hybrid.
Executed software comparisons and calculated bounds · 12 October 2026
FI compared ways to store calculation records while keeping the same required output, checks and record behavior. The smaller formats saved memory, but timing depended on the comparison. A separate signal-recording calculation exceeded its frame budget.
A packed, ordered snapshot used less traced Python memory in all 16 matched groups. The detailed record was faster in six groups; two comparisons were uncertain. Against a second read-only format, eight timing comparisons were uncertain.
The snapshot preserves the complete ordered record for reading. It gives up persistent edits, object identity, live changes, custom traces and the full list interface.
One specified validation job needs at least 16,896 recording units per frame to retain the unchanged record. Its budget is 8,192 units.
These are recording-work units from a fixed, uncalibrated model, rather than processor clock cycles.
The matched warm-service comparison includes creating the record, numerical guards, carrying state, decoding, validation, integrity checks and reading the complete record. Setup and priming are reported separately.
An earlier counts-only record reduced traced memory in eight matched groups and passed the timing rule in six; two timing comparisons remained uncertain. That record loses the required ordered journal.
The signal job stores 90,112 raw bytes per frame, then requires encoding, decoding and a full comparison. Even ideal raw capacity needs three parallel work lanes; charging for the actual record raises that to four. Scheduling the work within each frame remains unresolved.
A separate amplifier test used two models with supplied coefficients. Only lag and gain were calibrated on the training capture, then held fixed for validation. Both fixed models failed on the retained validation capture, which had already been seen. The provider’s use of the training, test and validation captures to prepare the coefficients remains unknown. One model had lower aggregate error, stated calculation work and coefficient storage; the other had lower peak error.
Costs against the existing FI baseline and on the target device remain unresolved.
Software study of supplied recordings · files checked 13 October 2026
FI compared predictions of amplifier output on three public ADL9006 recordings that had already been seen. For each recording, an early segment was used to fit and choose a model; 252,922 later points were then scored. The study covered 36 combinations of recording and method. Each combination ran in five fresh computer processes, giving 180 cost observations.
Aggregate error is the sum of squared prediction errors divided by the sum of squared recorded-signal values. Peak error is the largest error at a single point, in the source file’s units. Model selection used only the early pilot segment.
| Recording | Model | Aggregate error ratio | Aggregate reduction vs cubic | Peak error / source units |
|---|---|---|---|---|
| Train | Cubic model | 0.00142174 | Reference | 0.147569 |
| Train | Early choice: Trimmed linear fit | 0.000877161 | 38.30% less | 1.11674 |
| Test | Cubic model | 0.00247137 | Reference | 0.163150 |
| Test | Early choice: Supplied history model | 0.000742779 | 69.94% less | 0.129689 |
| Val | Cubic model | 0.00339548 | Reference | 0.142971 |
| Val | Early choice: Trimmed linear fit | 0.000939458 | 72.33% less | 1.33466 |
The selected models lowered aggregate error on all three recordings compared with cubic. Train and Val paid for that improvement with larger peak errors: about 1.12 and 1.33, compared with about 0.148 and 0.143 for cubic. On Test, the selected supplied history model lowered both errors.
Each row below records one fresh process. Time runs from launch to exit, including startup, fitting, prediction, required records and readback. Peak resident RAM includes Python and the numerical libraries. Retained storage counts the required inputs, complete outputs and work record once. The observing parent process and the equipment that captured the recordings are outside this software job.
| Recording / block | Choice | Cold time / s | Peak resident RAM | Required inputs | Outputs + manifest | Work record | Total retained |
|---|---|---|---|---|---|---|---|
| Test / 1 | Cubic | 0.252347 | 89,288,704 B | 8,134,355 B | 8,198,081 B | 3,445 B | 16,335,881 B |
| Test / 1 | Early choice | 0.323008 | 89,792,512 B | 8,134,355 B | 8,310,766 B | 3,552 B | 16,448,673 B |
| Test / 2 | Cubic | 0.205573 | 88,920,064 B | 8,134,355 B | 8,198,081 B | 3,445 B | 16,335,881 B |
| Test / 2 | Early choice | 0.361750 | 89,964,544 B | 8,134,355 B | 8,310,766 B | 3,551 B | 16,448,672 B |
| Test / 3 | Cubic | 0.203359 | 89,305,088 B | 8,134,355 B | 8,198,081 B | 3,444 B | 16,335,880 B |
| Test / 3 | Early choice | 0.349993 | 90,083,328 B | 8,134,355 B | 8,310,766 B | 3,551 B | 16,448,672 B |
| Test / 4 | Cubic | 0.207724 | 89,243,648 B | 8,134,355 B | 8,198,081 B | 3,444 B | 16,335,880 B |
| Test / 4 | Early choice | 0.369637 | 89,919,488 B | 8,134,355 B | 8,310,766 B | 3,548 B | 16,448,669 B |
| Test / 5 | Cubic | 0.206757 | 89,403,392 B | 8,134,355 B | 8,198,081 B | 3,443 B | 16,335,879 B |
| Test / 5 | Early choice | 0.367289 | 89,681,920 B | 8,134,355 B | 8,310,766 B | 3,548 B | 16,448,669 B |
| Train / 1 | Cubic | 0.196495 | 88,965,120 B | 8,134,738 B | 8,198,102 B | 3,451 B | 16,336,291 B |
| Train / 1 | Early choice | 0.561924 | 108,892,160 B | 8,134,738 B | 8,321,672 B | 8,794 B | 16,465,204 B |
| Train / 2 | Cubic | 0.201716 | 89,362,432 B | 8,134,738 B | 8,198,102 B | 3,449 B | 16,336,289 B |
| Train / 2 | Early choice | 0.547998 | 108,781,568 B | 8,134,738 B | 8,321,672 B | 8,793 B | 16,465,203 B |
| Train / 3 | Cubic | 0.196590 | 89,219,072 B | 8,134,738 B | 8,198,102 B | 3,454 B | 16,336,294 B |
| Train / 3 | Early choice | 0.567331 | 108,822,528 B | 8,134,738 B | 8,321,672 B | 8,793 B | 16,465,203 B |
| Train / 4 | Cubic | 0.202817 | 89,219,072 B | 8,134,738 B | 8,198,102 B | 3,454 B | 16,336,294 B |
| Train / 4 | Early choice | 0.572168 | 109,109,248 B | 8,134,738 B | 8,321,672 B | 8,795 B | 16,465,205 B |
| Train / 5 | Cubic | 0.217414 | 89,042,944 B | 8,134,738 B | 8,198,102 B | 3,452 B | 16,336,292 B |
| Train / 5 | Early choice | 0.606426 | 109,076,480 B | 8,134,738 B | 8,321,672 B | 8,793 B | 16,465,203 B |
| Val / 1 | Cubic | 0.194687 | 89,251,840 B | 8,135,874 B | 8,198,086 B | 3,448 B | 16,337,408 B |
| Val / 1 | Early choice | 0.550149 | 108,761,088 B | 8,135,874 B | 8,321,584 B | 8,792 B | 16,466,250 B |
| Val / 2 | Cubic | 0.195661 | 89,083,904 B | 8,135,874 B | 8,198,086 B | 3,447 B | 16,337,407 B |
| Val / 2 | Early choice | 0.540238 | 109,109,248 B | 8,135,874 B | 8,321,584 B | 8,790 B | 16,466,248 B |
| Val / 3 | Cubic | 0.207659 | 88,956,928 B | 8,135,874 B | 8,198,086 B | 3,444 B | 16,337,404 B |
| Val / 3 | Early choice | 0.563162 | 108,945,408 B | 8,135,874 B | 8,321,584 B | 8,793 B | 16,466,251 B |
| Val / 4 | Cubic | 0.202996 | 89,116,672 B | 8,135,874 B | 8,198,086 B | 3,447 B | 16,337,407 B |
| Val / 4 | Early choice | 0.585004 | 108,904,448 B | 8,135,874 B | 8,321,584 B | 8,792 B | 16,466,250 B |
| Val / 5 | Cubic | 0.212317 | 89,194,496 B | 8,135,874 B | 8,198,086 B | 3,448 B | 16,337,408 B |
| Val / 5 | Early choice | 0.587658 | 108,937,216 B | 8,135,874 B | 8,321,584 B | 8,794 B | 16,466,252 B |
The full record contains all 36 settings and 180 process-cost observations. Mean times and maximum memory values summarize separate observations. In the five-block paired analysis, timing remained uncertain in 138 of 396 directed method comparisons. Although the selector chose from early data, a different penalty method achieved lower aggregate error on the later Train and Val points.
Trimming weak directions in the linear fit, or penalizing large fitted coefficients, lowered both errors against the untreated history-model control on each recording. Train and Val still had much higher peaks than cubic. The tested large penalty, with relative strength 0.01, raised aggregate error to about 0.0170–0.0176 and peak error to 0.398–0.476. The supplied history model with calibrated gain also did worse than cubic on Val.
The trimmed fit uses the technical method TSVD with a relative cutoff of 0.001. The history models still store and evaluate 84 coefficient slots even when fewer fit directions are retained.
The pilot fits and chooses a model separately for each recording, with that work included in its costs. In the earlier test, a model fixed on Train failed when transferred to Val over a different scored range. The supplied model’s fitting and capture choices remain unknown. Its sampling descriptions conflict—100 MHz and 200 MHz—and the original evaluation and alignment rules have not been recovered.
These are ordinary fitting methods. A distinct FI implementation and the buyer’s acceptance limits have yet to be defined. This ADL9006 study and the SKY85747-11 radio comparison below use different error measures.
The original supplied archive is complete locally. Independent Windows checks accepted all 36 settings, 180 original observations, 396 comparisons and 39 volumes of complete point-by-point workings. Fresh runs of the original companion and an isolated moved copy each passed all 18 cells using both exact evidence archives. Those checks verified the files, arithmetic and portability; the process-cost observations came from the original host.
Named Wi-Fi transmit-path calculation · 12 October 2026
The Skyworks SKY85747-11 datasheet gives two Wi-Fi operating points with different output levels and error limits. At the lower output, a calculation leaves room for added processing error under the signal-reference assumptions below.
The datasheet lists +12 dBm output with −47 dB error and +16 dBm output with −43 dB error for 802.11ax MCS11 HE80 at 5 V and 25 °C. A job requiring +16 dBm rejects the +12 dBm operating point because it delivers less RF output. The lower RF output is a service loss; supply-power saving remains unquantified.
With the same signal reference, timing, corrections and normalization for all errors, the −47 dB source limit allows at most 0.0026126 added normalized RMS error while retaining a −43 dB total limit. RMS means root mean square, a measure of signal size. The allowance is about −51.6585 dB. It uses the triangle bound to cover the worst alignment between the source and added errors.
At a source error of −43 dB, no guaranteed added-error allowance remains. Adding squared errors would permit a larger allowance only if their cross-term were zero in the same norm. Statistical independence alone does not prove that condition for a finite recording. The datasheet leaves the exact error-measurement setup unresolved, so the common-reference assumption remains necessary.
At +16 dBm average output on ANT, the datasheet’s coupling limits imply −3 to +0.5 dBm average at CPLR, the feedback port, if the output and coupling limits share a power reference, impedance and bandwidth. Receiver headroom remains unresolved: waveform peaks, bandwidth, path loss, gain and linear input limits have not been matched.
Conventional designs can use the same integrated feedback coupler. Current draw has not been matched at these exact output and quality conditions. Feedback reception, conversion, processing and thermal costs remain unquantified.
APPLICATION AND QUALIFICATION PLAN
The 10 October application and qualification documents passed their fixed review criteria, and the complete reviewed checkpoint was delivered with its source and review records.
The application review left three inputs undefined: the useful output, operating task and required margin. Checks of the implementation remain open.
The reviewed FI and conventional candidates use identical operative source; their source comparison ties.
Current research statusRECORDER STORAGE · RECOVERY · COMPUTING / 8 OCTOBER 2026
The proposed layout keeps all 2,592,000 records from 30 days of one reading per second, with two durable copies and timing evidence for every record. It reserves less storage and reduces reads and writes during normal recording.
The design calculations leave more storage available around the same history and reduce the data read during routine restart. Restart time and installed energy remain unmeasured.
| Metric | Earlier design | Revised design | Practical change |
|---|---|---|---|
| Reserved recorder storage | 1,153,112,064 B | 862,808,256 B | 25.18% less reserved recorder storage |
| Recorder + complete input-history storage | 1,453,784,064 B | 1,163,480,256 B | 19.97% less for recorder and input-history storage |
| Normal capture writes | 580,608,000 B | 518,400,000 B | 10.71% fewer written bytes |
| Normal capture reads | 1,410,048,000 B | 1,161,216,000 B | 17.65% fewer read bytes |
| Data read on routine restart | 656,580,608 B | 8,391,072 B | 98.72% fewer read bytes; restart time unmeasured |
| Checksum work for timing records | 1,658,880,000 bit-level checksum steps | 663,552,000 bit-level checksum steps | 60% fewer bit-level checksum steps for timing records |
| Requests to save writes durably | 15,552,000 | 15,552,000 | Unchanged; six calls per record |
| Complete exported recording | 228,096,016 B | 228,096,016 B | Complete history and final state retained |
Storing shared identification once reduces each record’s timing data from 48 to 24 bytes. The layout also reserves less extra storage on the recorder. The complete 30-day history remains available for export and review.
Conventional software can implement these same layout changes.
Routine restart finds where recording stopped without rereading the entire history. It assumes previously checked data stays unchanged and postpones the full corruption scan.
The complete diagnostic scan remains available. It reads 594,374,304 bytes before saving the restart and final-state records. The number of requests to save writes durably stays unchanged.
| Metric | Current design budget | What determines the device benefit |
|---|---|---|
| Storage parts | The raw-capacity calculation gives six → five chips with the same complete input history, or five → four for recorder storage alone. | Those capacities permit the lower count. Protection against interrupted writes and removal of actual parts remain unresolved. |
| Weight | Published computer weights: 560 → 224 g, a 336 g difference. | A saving of at least 250 g after installation allows at most 86 g for extra parts and adverse weight variation. |
| Size | The computer’s outer-box volume falls by 0.109404 L, while one compared dimension grows by 8 mm. | The installed layout remains to be worked out. |
| Power, heat and life | Whole-device input energy remains unmeasured. | Recording, checks, idle, faults, restart, recharge and export energy remain unmeasured in this comparison. |
| Compute and speed | 60% less checksum work for timing records; 98.72% fewer routine recovery read bytes. | The simple 1 MHz path needs at least 67.108864 seconds just to transfer the full control-data area. It therefore fails the five-second restart target. |
| Range and interfaces | The recording task still requires two Ethernet ports. | Wired reach remains unchanged in the storage comparison. |
| Cost | The complete cost includes data acquisition, the receiving computer, power, backup hardware, engineering, installation and support. | Purchase-price and lifetime-cost comparisons remain open. |
Recorder saving: (1,153,112,064 − 862,808,256) ÷ 1,153,112,064 × 100 = 25.1756804098%. Including the same 300,672,000-byte input-history store in both designs gives 1,453,784,064 → 1,163,480,256 bytes, or 19.9688396089% less combined reserved storage. The complete exported recording remains 228,096,016 bytes, with verification and computer overhead additional.
The published address and page counts imply 268,435,456 bytes per chip. Five chips provide 1,342,177,280 bytes, which fits the revised recorder-plus-input-history allocation but falls short of the earlier one. The datasheet’s other sector and block counts disagree with this capacity. Usable capacity and protection against interrupted writes remain unresolved.
The recording task uses 64 arbitrary payload bytes, an 84-byte wire frame and an 88-byte stored record at 1 Hz for 30 days. It requires two durable logs before acknowledgment, exact full output, a one-second commit target, a five-second restart target and 0.1-second source-time accuracy. The conditions remain 0–40°C, 5–95% noncondensing humidity and allowed outages up to 60 seconds. No finite fault-count limit or minimum recharge gap is assumed.
The calculated fast restart assumes a correctly identified recording session, one writer and durable storage that neither silently changes nor returns old data. The service still requires continuous recording and accurate timekeeping through the specified outages. The review covers the source design, arithmetic and resource budget.
Technical reference: requirements and all 37 recovery calculations
REPORT CALCULATIONS / DESIGN COMPARISON
fewer expression evaluations
3,194,940 before
→ 2,457,660 after
Reusing exact intermediate values removes 737,280 repeated expression evaluations from this report design.
separate checker retained
The calculation and checker each keep their own saved intermediate values. They repeat less arithmetic while the checker remains independent.
additional FI arithmetic reduction
Caching means keeping intermediate answers in memory for reuse.
A conventional implementation using the same cache reaches the same arithmetic count.
These figures compare the arithmetic used to build the reports.
The count covers five reports, three jobs, two states and 4,096 sample pairs: 122,880 pairs per calculation path. The original calculation and checker use 26 rational-expression operations per pair; with caching they use 20. Both counts include 60 final divisions: 3,194,940 → 2,457,660. The reduction is 737,280 ÷ 3,194,940 = 23.0764897%.
The report-arithmetic count falls by 23.08%.
Technical reference: exact arithmetic countALUMINUM SUPPORT / DESIGN COMPARISON / 7 OCTOBER 2026
Two cutouts remove 116.51 g of support weight, or 35.96%, using nominal dimensions and typical density. The conventional and FI-assisted designs use identical hardware. Their installed performance remains unresolved.
| Decision | Supported result | What it means |
|---|---|---|
| Nominal support weight | 324 → 207.4851557911 g | 35.9613716694% less support mass, at typical density. |
| Outer installation dimensions | 200 × 150 × 13 mm in both designs | Unchanged outer installation dimensions. |
| Conservative new-build saving | At least 63.39 g − D | Conditional on all proposed dimensional, material and manufacturing controls. |
| Modifying the same retained blank | At least 105.75 g − D | Same-stock cancellation case; independent new builds use the separate 63.39 g − D bound. |
| FI vs capable ordinary design | Same B/C hardware | Identical proposed hardware. Design-work and lifecycle costs remain open. |
D is the weight of all permanent additions: finishes, guards, fasteners, cables, cooling and backup items. Under the proposed controls, D below 63.39 g guarantees a positive mass saving in a new build. For changes to the same blank, that bound is 105.75 g.
At or above these added-mass budgets, the lower bounds leave the actual saving unresolved.
Direct placement is an ordinary alternative for installations without a raised-support requirement.
Direct placement’s contact, cord and thermal conditions await qualification.
Nominal solid material volume changes from 120,000 mm³ to 76,846.35399670615 mm³. With typical density 2,700 kg/m³, mass = volume × 0.0027 g/mm³.
Full deck: 120,000 × 0.0027 = 324 g
Windowed deck: 76,846.35399670615 × 0.0027 = 207.4851557911 g
Reduction: (324 − 207.4851557911) ÷ 324 × 100 = 35.9613716694%
The controlled-design theorem uses proposed density bounds of 2,500–2,900 kg/m³, stiffness of at least 65,000 MPa and yield strength of at least 240 MPa, together with dimensional and manufacturing controls.
The intact adapter, leads and other common items lack a specified total mass. The difference calculation assumes identical common parts on both sides.
Remaining inputs include the actual raised-support requirement, accepted stock and manufacturing controls, complete load and cable identity, contact and stability, approved installation conditions, coupled thermal and eight-hour operating budgets, and lifecycle quotes.
The estimate uses the proposed geometry, material bounds and manufacturing conditions.
Technical reference: support geometry and mass calculationSENSOR READING PLANS
Across 12 selected cases, meeting the old equal-plan variance limit took 23.7847% fewer readings on average. The other choice was to keep the same reading count: modeled variance then fell 26.2972% on average. Variance measures how much the combined answer varies.
Exact greedy allocation and full search matched FI in every selected case. The model assumes independent readings, fixed per-reading variance, equal reading cost and no shared drift or systematic bias.
A separate energy scenario assigns 50% of original energy to readings and 3% to added processing. Eight selected cases exceed a 3% net saving, spanning 3.25–23.04%. One further case saves 1.17%; three equal-noise cases use 3% more. The calculation uses the stated energy-share assumptions.
Application fit: repeated sensing with acquisition-heavy energy use and unequal channel noise.
CALCULATION WORK
Adding each case’s median time gives 3.54% less time than the prior FI hybrid. Four of ten input families improved; six became slower.
The 15 October independent AI accounting review confirms that FI was slower than capable ordinary gmpy2 in all 26 preserved first-call and warm timing groups. The separate H22 study covers 2,500 cases against the prior FI hybrid.
Review cutoff: 17 October 2026. Recorder and support calculations retain their 8 and 7 October source dates.
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