FI Systems, CorpEfficiency is Everything

RESEARCH & PATENT STATUS / 17 OCTOBER 2026

Current work.

What we’re working on and what we’ve learned.

FI develops tools for sensing, recording, calculations and control. The saved evidence includes mathematical models, software comparisons, preliminary placed-and-routed filter-core results and document review.

LATEST SOURCE REVIEW / 17 OCTOBER 2026

Shared scheduling saves storage but misses the tight deadline.

Independent review checked 2,160 complete protocol jobs across 120 named references and all 1,440 fixed design candidates. All 1,440 candidates miss the saved tight deadline. The separate strict core-floor test leaves 15 candidates unresolved.

Next work is to complete the energy ledgers and include the cost of a circuit that calculates each CRC byte.

Review scope, independent verdict and exact sources →

Joint model and latest functional stage · review cutoff 17 October 2026

Complete reference-job results.

The complete-job model counts retained, removed, added and shared costs once. Both FI and the strongest tested ordinary controls receive compatible ordinary improvements. The results apply to the specified computational jobs, assumed energy laws and service boundaries. Here, nominal means the main modeled operating point.

  • Required kernel and wrapper work
  • Host formatting, DMA and complete readback
  • Program/state storage, decoding and configured preparation
  • Clock, idle, recovery and retained external loads
  • Supply losses and shared costs counted once

Complete-job cumulative study

Finished bounded model review: all 120 references compared, with 13 nominal wins, 100 ties and 7 unmatched against the strongest tested ordinary controls. No strict robust or tight-inclusive positive-saving winner. Shared and added costs are counted in the joint ledger.

Guarded-filter functional simulation

The guarded implementation completed 12 finite vendor-software simulation profiles without annotated route delays. Function/state checks passed and all six intended fault controls were detected. Public latency is 23 clock cycles, 16 more than the prior seven-clock source. Mapped timing, routed power and new whole-device savings remain unqualified.

The earlier backend’s seven-clock result remains in the historical record. The newer guarded source has 23 clocks of functional latency; its power and timing remain unqualified.

The best nominal reference combines compact streaming, clock-gated logic and a one-byte DMA wrapper in one cost calculation. The FIR, recorder and sensing studies have separate workloads and budgets.

The 13 nominal energy gains and their tradeoffs

Rows are ordered by nominal energy saving against the strongest tested ordinary control. Every row fails the registered test for a positive saving across the required conditions. The last column shows the worst tested energy change for that same nominal installation.

Reference jobNominal energy savedCompletion-time changeWorst tested energy change
D027 · Low-power Wi-Fi client electronics0.2563%+51.49%+0.4356% energy
D050 · Airframe health-data reduction0.1259%+4.07%+1.1896% energy
D095 · GNSS interference monitoring0.1259%+4.07%+1.1896% energy
D037 · Wearable sensor hub0.1242%-28.70%+1.1896% energy
D076 · Rail traction condition monitoring0.0862%+4.07%+0.8152% energy
D118 · Seismic field-array data pipeline0.0862%+4.07%+0.8152% energy
D120 · Observatory adaptive-optics actuation0.0808%+33.25%+1.4747% energy
D043 · Spacecraft payload telemetry reduction0.0594%+3.95%+0.9803% energy
D099 · Public-safety radio evidence recorder0.0309%+3.95%+0.5095% energy
D030 · RF instrument waveform linearization0.0308%+65.84%+0.0968% energy
D019 · Magnetic-bearing controller model0.0103%+43.01%+0.2022% energy
D015 · BLDC commutation controller0.0035%+37.37%+0.0679% energy
D072 · EV traction-inverter control0.0009%+37.74%+0.0170% energy

The best nominal Wi-Fi reference finishes within its 8 ms limit and fails the separate 1 microsecond stress limit. No fixed candidate met both positive-saving and feasibility requirements across the full core plus tight grid. Seven comparisons have missing baselines or feasibility gaps, so their saving percentages remain unavailable.

Separate recorder, sensor and phone budgets

The reviewed recorder allocation falls 19.96884% when the same full input history is included: 1,453,784,064 → 1,163,480,256 bytes. Its 25.17568% recorder-only reduction removes the same 290,303,808 bytes. Writes fall 10.7143%, reads 17.6471% and timing-record checksum steps 60%; these are separate axes. Required commit/restart, recovery, durability, clock and physical service remain to be qualified for a complete installation.

The sensing energy model includes a 50% reading-energy share and 3% planning cost. Eight selected cases save 3.25–23.04% versus equal counts; another saves 1.17%, while three equal-noise cases cost 3% more. Exact ordinary planners match the allocation.

If sensing is 20% of whole-phone energy and the other 80% stays fixed with no further costs, the selected sensing range becomes 0.65–4.61% less phone energy and 0.65–4.83% longer battery life with the same battery. Battery downsizing is an alternative use of the saving.

Application budgets for every target

Concise joint results and product coverage · All 120 references; cost ledgers for the 13 nominal wins

Matched modeled power · independent AI review · 16 October 2026

2.82% lower modeled active FPGA power.

Vivado’s power model puts FI’s hybrid 81-tap receive-channel filter at 310 mW while active, compared with 319 mW for the selected vendor transposed mapping at 25°C. Both use an AMD Artix-7 xc7a35tcpg236-1 FPGA. The modeled reduction is 9 mW, or 2.82%, of total active FPGA power. At 85°C, 424 → 415 mW gives a 2.12% reduction.

Same declared filter jobSelected vendor mappingFI hybrid
Active total power, 25°C319 mW310 mW
Idle total power, 25°C161 mW162 mW
Active total power, 85°C424 mW415 mW
Idle total power, 85°C266 mW267 mW
Active dynamic power247.5 mW238.5 mW
Idle dynamic power93 mW93 mW
Logic tables / ordinary registers48 / 330964 / 929
DSP arithmetic blocks / slices81 / 16240 / 579
Latency16 clock cycles46 clock cycles

FI uses 50.62% fewer DSP arithmetic blocks, trading them for about 20.08 times as many logic tables and 2.82 times as many ordinary registers. Both designs target 100 million real samples per second at 100 MHz and fit the declared 512-cycle latency ceiling. Their implementation remains to be qualified.

What it could mean for a device

Suppose the original 319 mW FPGA accounts for 25% of a device’s 1.276 W active power. Substituting the modeled 310 mW FPGA gives 1.267 W, a reduction of 0.7053%, rounded to 0.71%. This budget holds all other power fixed and adds no integration power. Idle FPGA power rises 1 mW.

Filter inputs, idle use and timing checks

The filter takes signed 16-bit Q15 inputs and 16-bit Q19 coefficients. Its exact output has 34 fractional bits, with no rounding. Synthetic 4,096-point I and Q traces were tested separately as real paths. Four signed vendor mappings were compared; the transposed area and speed versions tied on the reported power rows. FI v046 takes 46 cycles, compared with 16 for the reference.

Vivado 2023.2.2 used typical process conditions at fixed 25°C or 85°C. Independent checks confirmed matching activity at the designs’ inputs and outputs; internal activity was inferred. The reported 2.82% total-active and 3.64% active-dynamic reductions use rounded report values. Model uncertainty is unquantified. The idle case holds the design in its reset-idle state.

Interpolating between the latest rounded active and idle totals gives a vendor-minus-FI difference of (10 × active fraction − 1) mW. That calculation breaks even at 10% active time. It excludes transitions, temperature changes and other integration costs. The reports are rounded to 1 mW, and uncertainty in the crossing is unquantified.

Routed functional checks passed and static timing reports were positive, but timing through the native ACOUT paths used by the design remains unresolved. The newer version with a common wrapper passed functional checks; it has no accepted routed power result yet.

The finished 120-reference joint study selected 13 nominal energy wins, 100 ties and seven unmatched comparisons, with no robust positive-saving winner.

Power values, calculations and source identities

Preliminary routed core results · independent AI review · 15 October 2026

A fixed filter uses fewer logic resources.

A digital filter combines recent inputs to produce each output. FI revised a fixed 16-tap finite impulse response (FIR) filter to use 199 logic tables instead of 339 and 503 ordinary registers instead of 538. Both versions use seven digital signal-processing blocks. Against the paired reference, the revised core uses 41.30% fewer logic tables and 6.51% fewer registers.

The target chip is an xc7a35tcpg236-1 field-programmable gate array (FPGA), whose logic can be configured. Its lookup tables (LUTs) hold small logic functions, registers hold values between clock steps, and digital signal-processing (DSP) blocks perform arithmetic. The counts below come from vendor tools for one filter core.

CoreLogic tablesOrdinary registersDSP blocks
Paired reference P03395387
Revised P9_logic31995037
Alternative P91654198

All three retain exact 26-bit outputs from 16-bit inputs, seven stages and one input per clock under a 100 MHz timing constraint. The alternative P9 trades fewer logic tables and registers for one extra DSP block.

Review, added costs and separate comparisons

Vendor tools routed each core in isolation to produce these preliminary counts. Independent AI review inspected the source reports, finite integer checks, register-transfer-level (RTL) simulations and width bounds. RTL describes how values move between circuit registers.

The tested isolation change added 16 logic tables and 48 ordinary registers to P9, which still used eight DSP blocks. Review accepted no useful isolation benefit for that integration.

P9_logic3 still lacks qualified activity-based power, throughput and wider product-fit results.

In a separate three-channel sensing model, 12 readings meet the old balanced 13-reading quality limit, but variance is 8.580858% above the optimized 13-reading plan. A capable ordinary exact planner can match the allocation. In a separate count-and-rail energy example, the combined change uses 8/1943 (0.411734%) more energy than the ordinary lower-rail option under a chosen 25% affected share and separate 1% plus 1% costs.

In the separate software accounting review, FI was slower than capable ordinary gmpy2 in all 26 preserved first-call and warm groups. H22 covers 2,500 cases against the prior FI hybrid.

Filter results, review scope and source identities

Executed software comparisons and calculated bounds · 12 October 2026

Smaller records, mixed timing results.

FI compared ways to store calculation records while keeping the same required output, checks and record behavior. The smaller formats saved memory, but timing depended on the comparison. A separate signal-recording calculation exceeded its frame budget.

Read-only calculation records

A packed, ordered snapshot used less traced Python memory in all 16 matched groups. The detailed record was faster in six groups; two comparisons were uncertain. Against a second read-only format, eight timing comparisons were uncertain.

The snapshot preserves the complete ordered record for reading. It gives up persistent edits, object identity, live changes, custom traces and the full list interface.

Signal-recording deadlines

One specified validation job needs at least 16,896 recording units per frame to retain the unchanged record. Its budget is 8,192 units.

These are recording-work units from a fixed, uncalibrated model, rather than processor clock cycles.

What the comparisons include

The matched warm-service comparison includes creating the record, numerical guards, carrying state, decoding, validation, integrity checks and reading the complete record. Setup and priming are reported separately.

An earlier counts-only record reduced traced memory in eight matched groups and passed the timing rule in six; two timing comparisons remained uncertain. That record loses the required ordered journal.

The signal job stores 90,112 raw bytes per frame, then requires encoding, decoding and a full comparison. Even ideal raw capacity needs three parallel work lanes; charging for the actual record raises that to four. Scheduling the work within each frame remains unresolved.

A separate amplifier test used two models with supplied coefficients. Only lag and gain were calibrated on the training capture, then held fixed for validation. Both fixed models failed on the retained validation capture, which had already been seen. The provider’s use of the training, test and validation captures to prepare the coefficients remains unknown. One model had lower aggregate error, stated calculation work and coefficient storage; the other had lower peak error.

Costs against the existing FI baseline and on the target device remain unresolved.

Software scope and result record

Software study of supplied recordings · files checked 13 October 2026

Lower overall error, larger peak errors.

FI compared predictions of amplifier output on three public ADL9006 recordings that had already been seen. For each recording, an early segment was used to fit and choose a model; 252,922 later points were then scored. The study covered 36 combinations of recording and method. Each combination ran in five fresh computer processes, giving 180 cost observations.

Aggregate error is the sum of squared prediction errors divided by the sum of squared recorded-signal values. Peak error is the largest error at a single point, in the source file’s units. Model selection used only the early pilot segment.

RecordingModelAggregate error ratioAggregate reduction vs cubicPeak error / source units
TrainCubic model0.00142174Reference0.147569
TrainEarly choice: Trimmed linear fit0.00087716138.30% less1.11674
TestCubic model0.00247137Reference0.163150
TestEarly choice: Supplied history model0.00074277969.94% less0.129689
ValCubic model0.00339548Reference0.142971
ValEarly choice: Trimmed linear fit0.00093945872.33% less1.33466

The selected models lowered aggregate error on all three recordings compared with cubic. Train and Val paid for that improvement with larger peak errors: about 1.12 and 1.33, compared with about 0.148 and 0.143 for cubic. On Test, the selected supplied history model lowered both errors.

Process costs and other models

Each row below records one fresh process. Time runs from launch to exit, including startup, fitting, prediction, required records and readback. Peak resident RAM includes Python and the numerical libraries. Retained storage counts the required inputs, complete outputs and work record once. The observing parent process and the equipment that captured the recordings are outside this software job.

Recording / blockChoiceCold time / sPeak resident RAMRequired inputsOutputs + manifestWork recordTotal retained
Test / 1Cubic0.25234789,288,704 B8,134,355 B8,198,081 B3,445 B16,335,881 B
Test / 1Early choice0.32300889,792,512 B8,134,355 B8,310,766 B3,552 B16,448,673 B
Test / 2Cubic0.20557388,920,064 B8,134,355 B8,198,081 B3,445 B16,335,881 B
Test / 2Early choice0.36175089,964,544 B8,134,355 B8,310,766 B3,551 B16,448,672 B
Test / 3Cubic0.20335989,305,088 B8,134,355 B8,198,081 B3,444 B16,335,880 B
Test / 3Early choice0.34999390,083,328 B8,134,355 B8,310,766 B3,551 B16,448,672 B
Test / 4Cubic0.20772489,243,648 B8,134,355 B8,198,081 B3,444 B16,335,880 B
Test / 4Early choice0.36963789,919,488 B8,134,355 B8,310,766 B3,548 B16,448,669 B
Test / 5Cubic0.20675789,403,392 B8,134,355 B8,198,081 B3,443 B16,335,879 B
Test / 5Early choice0.36728989,681,920 B8,134,355 B8,310,766 B3,548 B16,448,669 B
Train / 1Cubic0.19649588,965,120 B8,134,738 B8,198,102 B3,451 B16,336,291 B
Train / 1Early choice0.561924108,892,160 B8,134,738 B8,321,672 B8,794 B16,465,204 B
Train / 2Cubic0.20171689,362,432 B8,134,738 B8,198,102 B3,449 B16,336,289 B
Train / 2Early choice0.547998108,781,568 B8,134,738 B8,321,672 B8,793 B16,465,203 B
Train / 3Cubic0.19659089,219,072 B8,134,738 B8,198,102 B3,454 B16,336,294 B
Train / 3Early choice0.567331108,822,528 B8,134,738 B8,321,672 B8,793 B16,465,203 B
Train / 4Cubic0.20281789,219,072 B8,134,738 B8,198,102 B3,454 B16,336,294 B
Train / 4Early choice0.572168109,109,248 B8,134,738 B8,321,672 B8,795 B16,465,205 B
Train / 5Cubic0.21741489,042,944 B8,134,738 B8,198,102 B3,452 B16,336,292 B
Train / 5Early choice0.606426109,076,480 B8,134,738 B8,321,672 B8,793 B16,465,203 B
Val / 1Cubic0.19468789,251,840 B8,135,874 B8,198,086 B3,448 B16,337,408 B
Val / 1Early choice0.550149108,761,088 B8,135,874 B8,321,584 B8,792 B16,466,250 B
Val / 2Cubic0.19566189,083,904 B8,135,874 B8,198,086 B3,447 B16,337,407 B
Val / 2Early choice0.540238109,109,248 B8,135,874 B8,321,584 B8,790 B16,466,248 B
Val / 3Cubic0.20765988,956,928 B8,135,874 B8,198,086 B3,444 B16,337,404 B
Val / 3Early choice0.563162108,945,408 B8,135,874 B8,321,584 B8,793 B16,466,251 B
Val / 4Cubic0.20299689,116,672 B8,135,874 B8,198,086 B3,447 B16,337,407 B
Val / 4Early choice0.585004108,904,448 B8,135,874 B8,321,584 B8,792 B16,466,250 B
Val / 5Cubic0.21231789,194,496 B8,135,874 B8,198,086 B3,448 B16,337,408 B
Val / 5Early choice0.587658108,937,216 B8,135,874 B8,321,584 B8,794 B16,466,252 B

The full record contains all 36 settings and 180 process-cost observations. Mean times and maximum memory values summarize separate observations. In the five-block paired analysis, timing remained uncertain in 138 of 396 directed method comparisons. Although the selector chose from early data, a different penalty method achieved lower aggregate error on the later Train and Val points.

Trimming weak directions in the linear fit, or penalizing large fitted coefficients, lowered both errors against the untreated history-model control on each recording. Train and Val still had much higher peaks than cubic. The tested large penalty, with relative strength 0.01, raised aggregate error to about 0.0170–0.0176 and peak error to 0.398–0.476. The supplied history model with calibrated gain also did worse than cubic on Val.

The trimmed fit uses the technical method TSVD with a relative cutoff of 0.001. The history models still store and evaluate 84 coefficient slots even when fewer fit directions are retained.

The pilot fits and chooses a model separately for each recording, with that work included in its costs. In the earlier test, a model fixed on Train failed when transferred to Val over a different scored range. The supplied model’s fitting and capture choices remain unknown. Its sampling descriptions conflict—100 MHz and 200 MHz—and the original evaluation and alignment rules have not been recovered.

These are ordinary fitting methods. A distinct FI implementation and the buyer’s acceptance limits have yet to be defined. This ADL9006 study and the SKY85747-11 radio comparison below use different error measures.

The original supplied archive is complete locally. Independent Windows checks accepted all 36 settings, 180 original observations, 396 comparisons and 39 volumes of complete point-by-point workings. Fresh runs of the original companion and an isolated moved copy each passed all 18 cells using both exact evidence archives. Those checks verified the files, arithmetic and portability; the process-cost observations came from the original host.

Complete software error and cost record

Named Wi-Fi transmit-path calculation · 12 October 2026

How much added radio error can fit?

The Skyworks SKY85747-11 datasheet gives two Wi-Fi operating points with different output levels and error limits. At the lower output, a calculation leaves room for added processing error under the signal-reference assumptions below.

Output levels and added-error allowance

The datasheet lists +12 dBm output with −47 dB error and +16 dBm output with −43 dB error for 802.11ax MCS11 HE80 at 5 V and 25 °C. A job requiring +16 dBm rejects the +12 dBm operating point because it delivers less RF output. The lower RF output is a service loss; supply-power saving remains unquantified.

With the same signal reference, timing, corrections and normalization for all errors, the −47 dB source limit allows at most 0.0026126 added normalized RMS error while retaining a −43 dB total limit. RMS means root mean square, a measure of signal size. The allowance is about −51.6585 dB. It uses the triangle bound to cover the worst alignment between the source and added errors.

At a source error of −43 dB, no guaranteed added-error allowance remains. Adding squared errors would permit a larger allowance only if their cross-term were zero in the same norm. Statistical independence alone does not prove that condition for a finite recording. The datasheet leaves the exact error-measurement setup unresolved, so the common-reference assumption remains necessary.

Feedback signal and unpriced costs

At +16 dBm average output on ANT, the datasheet’s coupling limits imply −3 to +0.5 dBm average at CPLR, the feedback port, if the output and coupling limits share a power reference, impedance and bandwidth. Receiver headroom remains unresolved: waveform peaks, bandwidth, path loss, gain and linear input limits have not been matched.

Conventional designs can use the same integrated feedback coupler. Current draw has not been matched at these exact output and quality conditions. Feedback reception, conversion, processing and thermal costs remain unquantified.

Named comparison and conditions

Source-rate calculation and software record model · 13 October 2026

A full record needs more than this link can carry.

The selected recording job uses one ADRV9009 observation-receiver chain at 200 MHz bandwidth and 245.76 million samples per second. The receiving computer stores each sample as two words: 16-bit I and 16-bit Q.

The I/Q values alone require 983.04 MB/s; the complete chosen record format requires 3,210.24 MB/s. After clock tolerances, one USB Gen1 lane has an encoded upper rate of about 500.150045 MB/s before packet and host costs. Under the stated rate and conservation assumptions, sustained delivery of this full format requires capturing for no more than about 15.5798% of the available time.

Burst service, failed cases and limits

The software model gives the receiver an ideal 400 MB/s service rate and a 4 MiB queue for records waiting to be delivered. MB means one million bytes; MiB means 1,048,576 bytes.

Declared model jobRequested framesRefused framesQueue at the horizonFull service
Ten 1 ms bursts across 100 ms2,40000 BKept all 2,400 frames
Same bursts, fixed 0.5–2.5 ms stall2,40000 BKept all frames in this one stall phase
Same bursts, fixed 0–20 ms stall2,4002,0870 B after drainFailed; later drain did not restore missing records
2 ms continuous capture, 10 ms capture-and-drain horizon480123776,899 BFailed; refused frames and unfinished delivery

Once a frame is refused for lack of capacity, the controller stops accepting new frames for the rest of that run. Every later planned frame is counted as refused, while queued records continue to drain whenever service is available. The model tests neither recovery nor renewed admission. The final queue contains accepted data still waiting for delivery when the chosen time window ends.

The ordinary R controller and candidate C follow the same generic rule and tie in every listed case. The successful 2 ms stall result covers one fixed position in the burst schedule.

The source-rate bound uses the admitted range of average clock rates. Physical arrival timing, jitter, rounding allowances and packet/host capacity costs remain open. The software work used generated synthetic records. The +16 dBm and +12 dBm radio-output jobs have separate service definitions.

Record-rate bounds, model results and exact sources

Independent AI document review completed · 10 October 2026

Application and qualification plan.

The 10 October review reconciled the proposed application, its source references and the plan for checking an implementation. The reviewed document set was delivered together with its source and review records.

Reviewed documents

The application and qualification documents passed their fixed review criteria.

Open application inputs

The application review left the useful output, operating task and required margin undefined. Checks of the implementation remain open.

The reviewed FI and conventional candidates use identical operative source; their source comparison ties.

See the evidence status

Three provisional drafts · latest recorded status: unfiled

The provisional patent drafts.

The current review set contains three specifications and nine drawing sheets. Their latest confirmed status is unfiled. The earlier application record is retained separately.

A

Checking thresholds across a domain from samples with a shared factor

Unfiled draft · specification and drawings prepared

9 specification pages · 2 drawing sheets

B

Differential Uncertainty and Precision Allocation

Unfiled draft · specification and drawings prepared

6 specification pages · 2 drawing sheets

C

Verified Coefficient Preparation and Controlled Execution

Unfiled draft · specification and drawings prepared

11 specification pages · 5 drawing sheets

The four earlier FI applications remain in the historical record.

QNUK / RESEARCH IN PROGRESS

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