{
  "schema": "FI_PUBLIC_FILTER_POWER_MODEL_20261016_R1",
  "evidence_type": "Preliminary matched vendor-tool power model; independent AI review with full timing qualification open",
  "workload": {
    "function": "81-tap receive-channel FIR, one real-valued path",
    "FPGA": "AMD Artix-7 xc7a35tcpg236-1",
    "tool": "Vivado 2023.2.2",
    "target_clock_MHz": 100,
    "target_real_samples_per_second": 100000000,
    "maximum_latency_cycles": 512,
    "input_bits": 16,
    "coefficient_bits": 16,
    "input_fraction_bits": 15,
    "coefficient_fraction_bits": 19,
    "output_fraction_bits": 34,
    "rounding": "none; full exact signed integer accumulation",
    "synthetic_samples_each_I_and_Q_separate": 4096
  },
  "comparison": {
    "candidate": "FI v046 hybrid",
    "reference": "AMD/Xilinx FIR Compiler fir_compiler_v7_2_21, transposed area and transposed speed tie among four signed settings; representative area only for bookkeeping.",
    "reference_scope": "Best of the four declared signed vendor mappings; transposed area and speed tie, not a global vendor optimum",
    "independent_verdict": "PASS_BOUNDED_ALL4_MATCHED_VENDOR_RESELECTION_AND_EXACT_POWER_GATE_INTEGRATION_NO_QUALIFIED_FI_WINNER"
  },
  "power_model_W": {
    "vendor_transposed": {
      "active_IQ_mean_W": {
        "25": {
          "dynamic_W": "0.2475",
          "total_W": "0.319",
          "static_W": "0.072"
        },
        "85": {
          "dynamic_W": "0.2475",
          "total_W": "0.424",
          "static_W": "0.177"
        }
      },
      "reset_idle_W": {
        "25": {
          "dynamic_W": "0.093",
          "total_W": "0.161",
          "static_W": "0.068"
        },
        "85": {
          "dynamic_W": "0.093",
          "total_W": "0.266",
          "static_W": "0.174"
        }
      }
    },
    "FI_hybrid": {
      "active_IQ_mean_W": {
        "25": {
          "dynamic_W": "0.2385",
          "total_W": "0.310",
          "static_W": "0.072"
        },
        "85": {
          "dynamic_W": "0.2385",
          "total_W": "0.415",
          "static_W": "0.177"
        }
      },
      "reset_idle_W": {
        "25": {
          "dynamic_W": "0.093",
          "total_W": "0.162",
          "static_W": "0.068"
        },
        "85": {
          "dynamic_W": "0.093",
          "total_W": "0.267",
          "static_W": "0.174"
        }
      }
    }
  },
  "resources_and_latency": {
    "fi_hybrid_full_mmcm6_r1": {
      "LUT": 964,
      "ordinary_FF": 929,
      "DSP": 40,
      "slices": 579,
      "BRAM_tiles": 0,
      "latency_cycles": 46,
      "checked_outputs": 26343,
      "reset_drops": 16
    },
    "vendor_trans_area_mmcm6_r1": {
      "LUT": 48,
      "ordinary_FF": 330,
      "DSP": 81,
      "slices": 162,
      "BRAM_tiles": 0,
      "latency_cycles": 16,
      "checked_outputs": 26343,
      "reset_drops": 16
    },
    "vendor_trans_speed_mmcm6_r1": {
      "LUT": 48,
      "ordinary_FF": 330,
      "DSP": 81,
      "slices": 162,
      "BRAM_tiles": 0,
      "latency_cycles": 16,
      "checked_outputs": 26343,
      "reset_drops": 16
    }
  },
  "calculated_reductions_percent": {
    "active_total_25C": 2.8213166144200628,
    "active_total_85C": 2.1226415094339623,
    "active_dynamic": 3.6363636363636362
  },
  "conditional_device_example": {
    "evidence_type": "New exact budget arithmetic, not an executed product model or measured device",
    "assumed_FPGA_share_of_active_device_power": 0.25,
    "device_active_before_W": 1.276,
    "device_active_after_W": 1.267,
    "active_device_power_reduction_percent": 0.7053291536050157,
    "other_active_power_and_integration_costs": "unchanged by assumption",
    "equation": "device reduction = FPGA power share × FPGA relative reduction",
    "limits": "No idle, transition, temperature-profile, battery, thermal-path, size, mass or range claim. Additional integration power must be below the 9mW modeled saving for a positive active benefit."
  },
  "duty_mixture_arithmetic": {
    "vendor_minus_FI_mW": "-1 + 10*d, where d is active fraction",
    "nominal_zero_active_fraction": 0.1,
    "status": "Interpolation of latest rounded active/reset-idle points only; not a robust threshold; no transition or changing-temperature costs"
  },
  "limitations": [
    "Power reports have 1mW granularity; active I/Q means can have 0.5mW steps. Arithmetic precision is not an uncertainty bound.",
    "Matched independently checked boundary activity; internal activity inferred; typical process; fixed25C/85C; same zero external output load.",
    "Reset-idle is not post-traffic idle. FI idle total power is1mW higher at both temperatures.",
    "FI requires more general logic/registers/slices and46 rather than16 latency cycles. Both fit512cycles but are not latency matched.",
    "Routed functional checks and positive static timing do not close missing consumed native ACOUT timing arcs. No qualified FI implementation winner.",
    "The newer common-wrapper functional pass has no accepted routed power result. The finished cumulative reference model has no robust positive-saving winner; its nominal outcomes remain scoped to declared assumed services.",
    "No physical result, commercial-product calibration, FI exclusivity or complete-device advantage established."
  ],
  "separate_portfolio_status": {
    "scope": "Completed frozen120-reference modeled R6 grid",
    "strict_robust_whole_device_winners": 0,
    "newer_R7": "Finished bounded model review: 13 nominal wins, 100 ties, seven unmatched and no robust positive-saving winner. The complete joint model does not compose this separate FIR power estimate."
  },
  "source_documents": [
    {
      "document": "Independent matched vendor selection and power-gate review R3",
      "sha256": "03e16d1bcffb1d284cd5984e45127a4abb7ad4c194fdbc95d3f3e8e34a96d0f1"
    },
    {
      "document": "Final hybrid findings R3",
      "sha256": "56df5b5ef434a8476986ab0252499eaf366544a88dd52b7fc660edc009d16e2d"
    }
  ],
  "latest_status_cutoff": "17 October 2026"
}